1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a circuit configuration of a semiconductor device including a CR oscillation circuit and a reset circuit.
2. Description of the Related Art
Traditionally, where the operating timing for a semiconductor device does not require the clock signal at high accuracy, in many cases, an external CR oscillation circuit with a capacitor and a resistor has been used as an inexpensive and simple oscillating circuit. As a reset signal generating circuit for defining the initial operation at power-on, an external reset circuit with a capacitor and a resistor has been also used.
FIG. 4 shows a circuit configuration of a conventional semiconductor device, i.e., a semiconductor device 1 including a capacitor C1 and a resistor R9 for CR oscillation and a capacitor C2 for generation of a reset signal. The CR oscillation circuit is configured as follows. The junction point of the capacitor C1 and the resistor R9 connected between a reference potential (GND) and a power supply voltage (V.sub.DD) is connected to a CR oscillation control circuit 2b of the semiconductor device 1 through a terminal T1. An output signal from the CR oscillation control circuit 2b passes through a buffer circuit 5 to provide an internal clock (hereinafter referred to as "CLK") signal for operating the semiconductor device 1. The discharge control of the capacitor C1 by the CR oscillation control circuit 2b permits the CR oscillation.
The reset circuit is configured as follows. One terminal of the capacitor C2 whose the other terminal is connected to the reference potential is connected to a reset control circuit 3b of the semiconductor device 1. An output signal from the reset control circuit 3b passes through a buffer circuit 7 to provide an internal reset (hereinafter referred to as "RST") signal for resetting the semiconductor device 1.
With no voltage applied from the power supply, the capacitor C2 is discharged so that the voltage at a terminal T2 is the reference potential. After power-on, the capacitor C2 is charged by the current flowing through a pull-up resistor (not shown) in the reset control circuit so that the voltage at the terminal T2 boosts gradually. When the voltage at the terminal T2 boosts to exceed a voltage set by the reset control circuit 3b, the reset control circuit 3b converts the level of the RST signal into the high level, thereby releasing the reset state of the semiconductor device 1.
Incidentally, the circuit configurations of the CR oscillation control circuit and the reset control circuit, which are disclosed in some technical literatures, are not described here. When the high accuracy in the oscillation frequency is not required, an oscillation circuit is frequently used in which the resistor 9 is provided within the semiconductor device 1 and only the capacitor C1 is externally provided.
The semiconductor device 1 as shown in FIG. 4 has the following defects. Although the device 1 can be realized by a simple circuit configuration, required are the terminal T1 connecting the capacitor C1 and the resistor R9 for CR oscillation and the terminal T2 connecting the capacitor C2 for generation of the reset signal. This increases the number of components externally equipped and requires the number of terminals for the semiconductor device 1. For this reason, a multi-pin package having a large number of terminals must be used, or otherwise the terminals for other functions must be canceled.
However, this gives rise to many problems. Namely, a large number of components externally equipped increase a substrate area for the external equipment and also cost because of the expense of the components themselves and management expense therefor. Use of a multi-pin package increases the production cost. Cancellation of the terminals for other functions makes it difficult to fulfill the required function sufficiently. Since the timing for generating the reset signal and the timing of the clock signal by oscillation are generated independently, the synchronization must be considered separately.